Engineering services
Silicon from architecture to tape-out — and past it.
We work across the full chip flow: system and micro-architecture, analog and mixed signal, RTL, verification, DFT and physical design — then bench validation and electrical characterisation once the parts come back.
ASIC · SoC · FPGA · Chiplets · MCP · Pre-silicon · Post-silicon
01 — Where silicon programmes are won
The tape-out date is decided long before the tape-out.
It is decided in architecture and verification.
Schedule risk in silicon concentrates in two places: an architecture that was never modelled against its real workload, and a verification plan that finds the interesting bugs in the last month rather than the first.
We staff both ends. Architecture work produces system models, virtual platforms and performance simulations early enough to change a decision; verification work brings structured methodology, custom verification IP for standard interfaces, formal techniques and FPGA emulation to bear before the design is frozen.
The implementation disciplines — RTL, DFT, analog and mixed signal, physical design — sit with the same group, so a timing or test problem found at floorplan does not have to travel back through three organisations to be fixed.
Talk to Zealogics02 — What the flow produces
One design database, carried the whole way down.
ARCHITECTURE · RTL · VERIFICATION · DFT · PHYSICAL · SILICON.
03 — What the work covers
Six disciplines across the full chip flow.
Application domains
Wireless and networking silicon
AI, ML and neuromorphic accelerators
Industrial and IoT devices
ADAS, automotive and battery management
Cloud acceleration and storage
Telecom and mobile
Design targets
Hardware architecture
System and micro-architecture for SoCs and ASICs — architecture brainstorming, complete system models, virtual platform development, performance simulation, early software platform enablement and the architecture and micro-architecture specifications that come out of it.
Analog and mixed signal
AMS design, layout, verification and production support across technology nodes, including ultra-low-power SoCs and integrated power management for automotive, avionics, industrial and consumer parts.
RTL design
RTL for core logic blocks and SoC integration, developed against the system architecture and closed against the design's performance, area and power constraints.
Design verification
Functional verification, low-power verification, formal verification and FPGA emulation, with custom verification IP for standard interfaces and a structured methodology behind the coverage numbers.
Design for test
DFT architecture that keeps test cost in proportion to design complexity — pattern generation, memory BIST with diagnostic and repair modes, and standalone test bench verification of the test logic itself.
Physical design
Floorplan and placement, clock tree and timing optimisation, power analysis and physical verification across planar and FinFET nodes, through to tape-out.
04 — Before and after the wafer
Pre-silicon decisions, post-silicon evidence.
The two halves are usually bought from different suppliers, which is why the questions raised in one so often go unanswered in the other.
01
Architecture and system model
A modelled architecture with performance simulation behind it, so the trade-offs are argued from numbers rather than from experience.
02
Verification plan and closure
Coverage model, verification IP, formal targets and emulation strategy — agreed at the start, tracked to closure.
03
Test architecture
A DFT strategy sized for the pattern count and tester time the programme can actually afford.
04
Timing, power and physical signoff
Floorplan, timing optimisation, power analysis and physical verification carried to a signoff a foundry will accept.
05
Bench validation
Silicon functionality validated across platforms, with bench validation and electrical characterisation rather than a functional smoke test.
06
Productisation support
Test strategy, characterisation data and the engineering support that takes a complex design from first silicon to a shippable part.
05 — How a programme runs
Five stages, with verification running through all of them.
Verification is drawn as a stage here for legibility. In practice it starts at architecture and does not stop until the part ships.
Architect
System and micro-architecture, modelling, performance simulation and the specifications that fall out of them.
Design
RTL for logic blocks and SoC integration, analog and mixed signal design and layout.
Verify
Functional, low-power and formal verification, verification IP and FPGA emulation against the coverage model.
Implement
DFT insertion, floorplan, placement, timing closure, power analysis and physical verification.
Validate silicon
Bench validation, electrical characterisation and productisation support once parts return.
06 — Where the disciplines meet
Architecture, RTL, test and physical design in one loop.
A PROBLEM FOUND AT FLOORPLAN GOES BACK ONE DESK.
07 — Sound familiar?
The conversations that start this work.
“We need a team that can take a block from RTL to signoff.”
Full implementation flow
“Verification is the critical path and it keeps moving.”
DV methodology and IP
“Our test cost per part is climbing with every node.”
DFT architecture
“The architecture was never modelled against the real workload.”
Performance simulation
“The analog block is the reason we cannot tape out.”
AMS design and layout
“First silicon is back and nobody owns bring-up.”
Post-silicon validation
08 — The rest of the practice
Five more engineering disciplines.
Programmes rarely stay inside one discipline. A tool that needs embedded firmware usually needs the mechanics, the harness and the line that builds it too.
Embed
Embedded Systems
Turn a product concept into hardware and the firmware that runs it — schematics, layout, bring-up, certification and the years of sustenance after.
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Connect
Factory Automation
Equipment software, SECS/GEM and GEM300 integration, EAP and MES connectivity, manufacturing data — and the intelligence layer built on top of them.
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Design
Mechanical Engineering
Product design and development, engineering analysis and simulation, model-based systems engineering, and the change management that keeps a design alive for a decade.
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Route
Electrical Engineering
Wiring harness design, 3D routing, schematics, bundling and segregation, power distribution and the build support that gets a harness onto the shop floor.
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Build
Manufacturing
PCB, turnkey, box build, harness and cleanroom assembly under the same engineering ownership as the design — with the test capability to prove what shipped.
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Have a problem worth solving?
Tell us which part of the flow is short.
Whether it is an architecture question, a verification backlog or a physical design team that needs depth for one tape-out, we scope to the gap rather than to the whole programme.